Archive for the ‘FPGA’ Category

Open High Definition Video Capture Card

February 21, 2010

Discrete Cosine Transform coefficients

The page I have created for this project over at is here

Here is an excerpt:

This project will capture High Definition Video 1280×720 at 30fps, and hopefully be capable of 60fps and maybe even 1080p. I intend to use a cheap FPGA, A HiSpeed USB PHY, and an Analog Devices Video A/D chip. I will nail down exact chip numbers later. The target platform driver and example code will be written for linux. This project is more a proof of concept and more for fun and excercise rather than to be practical. But I will take any advice and help that I can get and who knows what we might create here. Entire BOM should be less than $40 but we’ll see.

Yes I know about the Hauppage HD-PVR or whatever its called that Capures Component video at 720p. The problem is that device uses H.264 encoding, which is just way too expensive to decode, it takes a Dual Core 1GHz Machine at 99%. It is also not totally open to hacking.

Current Status

  • 04/06/2010 Adding the FPGA to the board now, external devboard is gone.  It will be a spartan3e 250 vq100 pkg.
  • 04/03/2010 Firewire Chip found that offers a High-speed parallel interface, TI TSB12LV32IPZ:
  • 03/25/2010 Mailing List has been added, here is the mailman link to subscribe:
  • 03/24/2010 USB Chip is the USB3250. Working on schematic capture and part selection.
  • 03/19/2010 USB Chip will likely be the USB3250, the USB3318 would be slightly more difficult to put into the UTMI core from opencores.
  • 03/12/2010 Chris has offered to help with the USB portion of the project
  • 03/11/2010 Project now has git hosting on git://
  • 03/11/2010 Added “How To Volunteer” section. Found this core that should work with the USB chip here:,usb
  • 03/09/2010 Created the ad9883a part and package in Eagle. I Began researching what it takes to get the USB3318 chip to work. I am also Considering maybe using the TSB41AB1 1394/Firewire chip. USB is a PITA to work with because of the protocol overhead. If we do Firewire, it will be in addition to USB.

I am in the planning/brainstorming stages, although I have been researching this for at least the last 6-8 months.

I have a working Forward/Reverse DCT algorithm in matlab (actually Gnu Octave) that can compress an image 5:1 with little loss in quality. I have also done much research on putting a DCT in hardware. Currently the DCT will be broken down into 2 stages, and all multiplies/adds will likely be done using a very parallel bit-wide pipeline to keep clock speeds high.

Data Bandwidth Issues
YUV422 720p data comes in at roughly 1280*720*30*16 = 443 MegaBits/s. HiSpeed USB is 480Mbits/s which, after taxes, is probably not enough. Note that 720p60 is twice that. Either way using the DCT and some Huffman coding along with other simple compression techniques we can squeeze the data down a little without hurting quality too bad. My goal is to get it down to 150Mbits/s

High Speed Logic Analyzer FPGA

August 6, 2008
Spartan 3e Sample Board

Spartan 3e Sample Board

Many others have had the idea to build a logic analyzer based on an FPGA. I have some novel ideas that make it much easier and much more practical to accomplish this, while keeping the features of a much more expensive LA. Some qualities that make this idea unique:

  • Save Development time on the PC end Dramatically
  • Use a slow speed PC Bus
  • Sample at whatever speed the FPGA can dish out (100MHz easily for the spartan series)

The design strategies which make this possible are:

  • Use the 216Kbits of internal Block RAM (27,000 bytes)
  • Only record changes, and time value on the inputs, (dramatically saving RAM space), also making it easy to create vcd files from this data
  • Use the PC serial port (UART + Level shifter) or ft232r
  • Create a vcd file from the vcd-like dump
  • Use gtkwave on a PC to view waveforms in the vcd file
GtkWave in action, viewing a simulation

GtkWave in action, viewing a simulation

Limitations and Tradeoffs

Unforunately, as with any engineering task, there are numerous trade-offs. This design maximizes usefulness for my standard logic analyzing needs like sniffing data on an i2s bus, or capturing a usart bit-stream.

  • The Spartan3e is only 3.3V tolerant without voltage translators.
  • We can only capture about 10,000 bit “events” or so (usually enough though).
  • Triggering will be kept simple to keep the overall design simple (wait for a low signal or high signal).
  • Uses independent clock, so it is asynchronous to any local clock on the device we are sampling.
  • Need a PC

The constant clock limits complexity on usart / rs232 interface. Otherwise a clock must be calculated at run-time, and this is not practical. I also do not want to be limited to sampling systems with clocks. I always try to practice Keep it Simple Dammit (KISD).

Design Parts

The Hardware

I intend to start this project out on an older Spartan 3e development board. I will first create a block diagram and some logic timing diagrams. The inputs will be double buffered by flip-flops to avoid metastability caused by setup/hold violations on the asynchronous inputs. We can’t get rid of all of this, but we can minimize it. This is a common “hack” for asynchronous inputs. Just google it and you’ll see.

This project will be published on

The UI Software

I will create a simple GUI to control the Logic Analyzer (reset, set trigger, dump data). This will be based on GTK in Linux using C and uses just the serial port, so this should be easily ported to MS windows. I know you can embed GtkWave into an app, we’ll see if I get that ambitious though. You will be able to name the signals here. Grouping of signals may be added at a later date. Grouping is a feature I would rarely use.

VCD File Generator

A VCD file is an ASCII based file in which only changes are recorded. The format is simple enough that we don’t need a special library to read/write to VCD. It consists of a small header with things like the date, simulation time, and signal names. My UI program will generate a dump and call this VCD generator program to convert it to a VCD. It should be pretty simple.


This design is intended to be open (source files and schematics are public) and anyone who is interested may contact me if they would like to help make it better or add features.

Sigma-Delta Modulation Primer Part II

June 30, 2007

UPDATE! Code now bypasses so16() function which would have caused errors for you.

Well here is the first order Sigma-Delta Modulation code for matlab or octave . You will need to download the wav file, or use one of your own that has audio near 16kHz sample rate, and has audio between the first 2000 and 10000 samples. I cannot currently post wav files because wordpress will not let me. If you don’t want to mess with wav’s then you can use the square wave version.

Click For Larger View:
Sigma-Delta Modulation

Go to: Right click on the Space Ghost clip (whatsup.wav) file and do a save as to the same directory as the code. I would provide a direct link but they don’t seem to allow hotlinking.

Here is the first order SDM code for a wav file (GNU Octave):

Created with Vim 7.0 command :TOhtml
%    firstOrderDSM.m
%    Implements a first order Sigma-Delta Modulator
%    Copyright 2007 Brian R Phelps
%    This program is free software; you can redistribute it and/or modify
%    it under the terms of the GNU General Public License as published by
%    the Free Software Foundation; either version 3 of the License, or
%    (at your option) any later version.
%    This program is distributed in the hope that it will be useful,
%    but WITHOUT ANY WARRANTY; without even the implied warranty of
%    GNU General Public License for more details.
%    You should have received a copy of the GNU General Public License
%    along with this program.  If not, see;

OSR=10;         % The over sampling rate
z1km1q = 0; % Initialize variables
z1km1 = 0;
% Scale the data to 16 bit "integers", hardware 
% in real life is integer or fixed point math
%returns scaled integers
for n=1:NumSamps
   for k=1:OSR  % Each sample is Oversampled OSR times
      % please see the diagram for an explanation for the following:
      z1(k) = z1km1;
      z1km1 = z1(k) + xn  - z1km1q;
      z1km1q = (z1km1 > 0) * 32766 - (z1km1 <= 0) * 32766;
      y(k+(n-1)*OSR) = (z1km1 > 0) - (z1km1 <= 0);

b=fir1(121,1/(OSR*2));  % A low pass filter is also an integrator (summer), 
                        % either way it is neccessary to recover the original signal
y=filter(b,1,y);        % This gets rid of the noise, which 
                        % most of which is moved out of the passband
y=decimate(y,OSR);      % Keep only 1/10 samples to get the 
                        % sample rate back down to original
plot(1:length(y),y );