Archive for August, 2008

High Speed Logic Analyzer FPGA

August 6, 2008
Spartan 3e Sample Board

Spartan 3e Sample Board

Many others have had the idea to build a logic analyzer based on an FPGA. I have some novel ideas that make it much easier and much more practical to accomplish this, while keeping the features of a much more expensive LA. Some qualities that make this idea unique:

  • Save Development time on the PC end Dramatically
  • Use a slow speed PC Bus
  • Sample at whatever speed the FPGA can dish out (100MHz easily for the spartan series)

The design strategies which make this possible are:

  • Use the 216Kbits of internal Block RAM (27,000 bytes)
  • Only record changes, and time value on the inputs, (dramatically saving RAM space), also making it easy to create vcd files from this data
  • Use the PC serial port (UART + Level shifter) or ft232r
  • Create a vcd file from the vcd-like dump
  • Use gtkwave on a PC to view waveforms in the vcd file
GtkWave in action, viewing a simulation

GtkWave in action, viewing a simulation

Limitations and Tradeoffs

Unforunately, as with any engineering task, there are numerous trade-offs. This design maximizes usefulness for my standard logic analyzing needs like sniffing data on an i2s bus, or capturing a usart bit-stream.

  • The Spartan3e is only 3.3V tolerant without voltage translators.
  • We can only capture about 10,000 bit “events” or so (usually enough though).
  • Triggering will be kept simple to keep the overall design simple (wait for a low signal or high signal).
  • Uses independent clock, so it is asynchronous to any local clock on the device we are sampling.
  • Need a PC

The constant clock limits complexity on usart / rs232 interface. Otherwise a clock must be calculated at run-time, and this is not practical. I also do not want to be limited to sampling systems with clocks. I always try to practice Keep it Simple Dammit (KISD).

Design Parts

The Hardware

I intend to start this project out on an older Spartan 3e development board. I will first create a block diagram and some logic timing diagrams. The inputs will be double buffered by flip-flops to avoid metastability caused by setup/hold violations on the asynchronous inputs. We can’t get rid of all of this, but we can minimize it. This is a common “hack” for asynchronous inputs. Just google it and you’ll see.

This project will be published on

The UI Software

I will create a simple GUI to control the Logic Analyzer (reset, set trigger, dump data). This will be based on GTK in Linux using C and uses just the serial port, so this should be easily ported to MS windows. I know you can embed GtkWave into an app, we’ll see if I get that ambitious though. You will be able to name the signals here. Grouping of signals may be added at a later date. Grouping is a feature I would rarely use.

VCD File Generator

A VCD file is an ASCII based file in which only changes are recorded. The format is simple enough that we don’t need a special library to read/write to VCD. It consists of a small header with things like the date, simulation time, and signal names. My UI program will generate a dump and call this VCD generator program to convert it to a VCD. It should be pretty simple.


This design is intended to be open (source files and schematics are public) and anyone who is interested may contact me if they would like to help make it better or add features.