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	<title>Comments on: High Speed Logic Analyzer FPGA</title>
	<atom:link href="http://electronjunkie.wordpress.com/2008/08/06/high-speed-logic-analyzer-fpga/feed/" rel="self" type="application/rss+xml" />
	<link>http://electronjunkie.wordpress.com/2008/08/06/high-speed-logic-analyzer-fpga/</link>
	<description>Electrical Engineering Theory, DSP, Linux And Embedded Systems (MCUs, FPGA/CPLD's)</description>
	<lastBuildDate>Thu, 18 Mar 2010 18:16:28 +0000</lastBuildDate>
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	<item>
		<title>By: electronjunkie</title>
		<link>http://electronjunkie.wordpress.com/2008/08/06/high-speed-logic-analyzer-fpga/#comment-203</link>
		<dc:creator><![CDATA[electronjunkie]]></dc:creator>
		<pubDate>Mon, 11 Jan 2010 22:06:23 +0000</pubDate>
		<guid isPermaLink="false">http://electronjunkie.wordpress.com/?p=47#comment-203</guid>
		<description><![CDATA[gtk-wave IS an excellent GUI for viewing and analyzing digital wave forms.  At least use its codebase.  Why reinvent the wheel?  I wrote a simple command line app for triggering and converting the data from the serial port to vcd data for gtk-wave.  I wrote nothing noteworthy, as I wound up not needing compression for my application, but I may need it in the future for an upcoming project.]]></description>
		<content:encoded><![CDATA[<p>gtk-wave IS an excellent GUI for viewing and analyzing digital wave forms.  At least use its codebase.  Why reinvent the wheel?  I wrote a simple command line app for triggering and converting the data from the serial port to vcd data for gtk-wave.  I wrote nothing noteworthy, as I wound up not needing compression for my application, but I may need it in the future for an upcoming project.</p>
]]></content:encoded>
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	<item>
		<title>By: Trygve Laugstøl</title>
		<link>http://electronjunkie.wordpress.com/2008/08/06/high-speed-logic-analyzer-fpga/#comment-202</link>
		<dc:creator><![CDATA[Trygve Laugstøl]]></dc:creator>
		<pubDate>Mon, 11 Jan 2010 21:52:50 +0000</pubDate>
		<guid isPermaLink="false">http://electronjunkie.wordpress.com/?p=47#comment-202</guid>
		<description><![CDATA[Hi

Did you complete this project? If so, what GUI did you use for your analyzer? I&#039;ve started writing a (generic) GUI for the Saleae Logic analyzer which I&#039;d like to spread and get more users of. It&#039;s still very nice, but should be quite portable between platforms and analyzer.

http://github.com/trygvis/infero

--
Trygve]]></description>
		<content:encoded><![CDATA[<p>Hi</p>
<p>Did you complete this project? If so, what GUI did you use for your analyzer? I&#8217;ve started writing a (generic) GUI for the Saleae Logic analyzer which I&#8217;d like to spread and get more users of. It&#8217;s still very nice, but should be quite portable between platforms and analyzer.</p>
<p><a href="http://github.com/trygvis/infero" rel="nofollow">http://github.com/trygvis/infero</a></p>
<p>&#8211;<br />
Trygve</p>
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	<item>
		<title>By: electronjunkie</title>
		<link>http://electronjunkie.wordpress.com/2008/08/06/high-speed-logic-analyzer-fpga/#comment-177</link>
		<dc:creator><![CDATA[electronjunkie]]></dc:creator>
		<pubDate>Tue, 02 Sep 2008 02:29:40 +0000</pubDate>
		<guid isPermaLink="false">http://electronjunkie.wordpress.com/?p=47#comment-177</guid>
		<description><![CDATA[Hi Peter,
Thank you for your encouragement.  Aside from studying (the relatively simple) vcd file format, I currently (only) have a couple of tables and finite state machines for implementing these ideas.  Unfortunately mid August to mid September is hell at work.  When things cut back a bit and I have more time, I&#039;ll post my code.  When things let up, I&#039;ll be happy to share some more of this project.  

I do expect the recording of changes only to save many kB of precious RAM.

-Brian]]></description>
		<content:encoded><![CDATA[<p>Hi Peter,<br />
Thank you for your encouragement.  Aside from studying (the relatively simple) vcd file format, I currently (only) have a couple of tables and finite state machines for implementing these ideas.  Unfortunately mid August to mid September is hell at work.  When things cut back a bit and I have more time, I&#8217;ll post my code.  When things let up, I&#8217;ll be happy to share some more of this project.  </p>
<p>I do expect the recording of changes only to save many kB of precious RAM.</p>
<p>-Brian</p>
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	</item>
	<item>
		<title>By: Peter Bašič</title>
		<link>http://electronjunkie.wordpress.com/2008/08/06/high-speed-logic-analyzer-fpga/#comment-176</link>
		<dc:creator><![CDATA[Peter Bašič]]></dc:creator>
		<pubDate>Mon, 01 Sep 2008 07:35:29 +0000</pubDate>
		<guid isPermaLink="false">http://electronjunkie.wordpress.com/?p=47#comment-176</guid>
		<description><![CDATA[Hi,

your LA looks very promising. There are really very smart ideas implemented. I would like to take a look at the source code and eventually contribute back. Can you provide a link to the source code?

Regards,
Peter]]></description>
		<content:encoded><![CDATA[<p>Hi,</p>
<p>your LA looks very promising. There are really very smart ideas implemented. I would like to take a look at the source code and eventually contribute back. Can you provide a link to the source code?</p>
<p>Regards,<br />
Peter</p>
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